"Cortex-A9 Single Core Processor".
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Its always possible the Linux sources are correct since the TI developers have access to non-public documentation.
The FreeBSD code needs some work to support this.Is this just declaring the device as capable of being an interrupt-controller?Variscite exist, but I dont own any and havent tested.Because Im listing the uarts in the order 3, 1, 2, 4 in the dts, they show up this way in the O/S uart3 - /dev/ttyu0 or /dev/cuau0 uart1 - /dev/ttyu1 or /dev/cuau1 uart2 - /dev/ttyu2 or /dev/cuau2 uart4 - /dev/ttyu3 or /dev/cuau3 Im listing.So I went to /sys/kernel/debug/omap_mux/ to change the MUX settings but the folder just contains another folder called board that is empty!Some notes from working.C compatible "ti, omap4-gpio From (1 Section.6.1, Table 25-17 The Linux omap4.dtsi uses a size of 0x200 for each bank which is sufficient if you look at the last register for each bank controller.#address-cells 1 #size-cells 1 Used in sys/arm/ti/ti_machdep.FreeBSD does not have an equivalent.Dts) that include this base omap443x.dtsi.Linux uses ti, omap4-i2c.And here is the breakdown, top level / #address-cells 1 #size-cells 1 compatible "ti, omap4430 "ti, omap4 interrupt-parent gic Description These two properties come from a skeleton.
Compatible "ti, omap4-i2c "ti, i2c" From (1) Section, Table 23-30 reg x100 From (1 Section.3.2, Table 17-2 interrupts 88 Used in sys/arm/ti/ti_i2c.c to enable the clock for this device as an offset from I2C0_CLK.
This is the region used circuit wizard for windows 7 for both PPI (private, per core) and SPI (shared peripheral) interrupt processing.
L2 cache controller (04 MB).
Our network-on-chip interconnect IP fabric is used as the main L3 interconnect within omap 4 platforms.Table A-6 from (3) has a description on where to read.Compatible "ti, omap4430-sdma "ti, sdma" From (1 Section.6.1, Table 16-22 reg 0x4A056000 0x1000 From (1 Section.3.2, Table 17-2 MA_IRQ_12 : sdma_IRQ_0 MA_IRQ_13 : sdma_IRQ_1 MA_IRQ_14 : sdma_IRQ_2 MA_IRQ_15 : sdma_IRQ_3 The FreeBSD values using a flat IRQ address space are interrupts gpio gpio.The omap4430 TRM is still at version."Mindspeed to Showcase the Industry's First ARM Cortex A9-based Communications Processor with Integrated DPI at 2013 CES".From the TRM, I think they are both wrong and that the correct size is [email protected] compatible "ti, omap4_prcm reg 0x4a306000 0x2000 0x4a004000 0x1000 0x4a008000 0x2000 0x4a30a000 0x0520 ; Description Used in compatible "ti, omap4_prcm" The register definitions are for [email protected] - device-level power and reset management [email protected] - device-level clock management 1 [email protected] - device-level clock management 2 [email protected]